1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to integrated circuits formed of multiple layers of circuits.
2. Description of the Prior Art
As the process size with which integrated circuits are manufactured has become smaller fault tolerance is becoming increasingly important factor in integrated circuit design. Furthermore, there is an increased problem of post-manufacture (field) failures of integrated circuits due to wear out caused by electromigration and oxide breakdown (among other factors). These failures are made worse by the difficulties related to manufacture-time burn-in; it is increasingly difficult to over-stress integrated circuits at manufacture-time to find integrated circuits that are likely to fail early in the field as such techniques incur too many false positives causing excessive yield loss. A further factor is the increasing uncertainty associated with manufactured structures: it is becoming increasingly difficult to be confident that measurement/test conditions are sufficiently like operating conditions to give valid information such that subsequent failures are often due to variability rather than any particular break-down effect.
It has been proposed to apply fault tolerance techniques more extensively within integrated circuits in order to render them more robust against the above types of problem. However, such traditional fault tolerance techniques require significant modification of the integrated circuit architecture of many designs representing a significant and disadvantageous cost. Furthermore, the use of such fault tolerance techniques (such as triple modular redundancy) tends to be expensive in the terms of the associated circuit overhead.